1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of issue control within multi-threaded in-order superscalar processors whereby instructions from a plurality of program threads are selected for issue to execution units.
2. Description of the Prior Art
It is known to provide multi-threaded out-of-order superscalar processors such as the Pentium4 with HyperThreading produced by Intel Corporation. These multi-threaded out-of-order processors are capable of a high instruction throughput by reducing the occurrence of situations in which no or few instructions are issued due to data dependencies or other circumstances. However, there is a disadvantageous degree of complexity and circuit overhead associated with such multi-threaded out-of-order superscalar processors rendering them unsuitable for some applications. As an example, such processors are not well suited for use in low cost, low power systems.
A known multi-threaded in-order superscalar processor is the Porthos network processor. This provides up to 32-thread support and employs an issue policy in which one instruction from each of three threads is issued in parallel. This issue policy is relatively simple and is effective in the network processor application area which is the target of the Porthos processor, but such an issue policy is not well suited to improve the single-thread performance.
As an example, one significant potential use of multi-threaded in-order superscalar processors is in executing program instructions from multiple program threads where at least one of the program threads has a high priority and at least one of the program threads has a low priority. In this circumstance, it is desirable that program instructions from the high priority threads are issued for execution in preference to those from the low priority threads. Nevertheless, it is desirable that the number of cycles needed to execute each instruction from the low priority thread should not become too high. One way of achieving this would be to use an aggressive instruction issue policy in which issue slots are allocated by trying to issue all instructions from the high priority thread first and then trying to issue the instructions from the low priority thread if there are any available issue slots left unused by the high priority thread. However, such an approach significantly increases hardware complexity within the issue stage in a disadvantageous manner and can introduce unwanted critical timing paths which can limit the cycle time of the issue unit.
A possible issue policy for multi-threaded in-order superscalar processors when the priorities are equal is a round-robin thread issue policy. When priority differences existed between threads, then the threads can be sorted by their priorities and then the issue logic can use the round-robin policy. A pure round-robin thread issue policy will tend to degrade the performance of a high priority thread. Conversely, a round-robin issue policy based upon sorted threads can starve a low priority thread of opportunities to issue instructions and according undesirably increase the cycles-per-instruction associated with the instructions from the low priority thread.
It is desirable to provide multi-threaded in-order superscalar processors with issue circuitry capable of maintaining a good performance for a high priority thread without sacrificing too much of the performance associated with the low priority thread and without adversely impacting the issue cycle time or introducing a disadvantageous degree of hardware complexity/cost.